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Component List
Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 1 of 2)
Board Designation
Featured Device
U60
Name
Stratix II FPGA
Description
EP2S60F672C5 or EP2S30F672C5 device with mounted
heat sink
User Interface
SW0 – SW3
D0 – D7
U8, U9
Memory
U35, U36
U5
U57
Connectors & Interfaces
U4, RJ1
J19, J27
PROTO1 (J11, J12, J13)
PROTO2 (J15, J16, J17)
CON3
J25
J24
J5
Configuration & Reset
U3
Push-button
switches
Individual LEDs
Seven-segment
LEDs
SRAM memory
Flash memory
SDRAM memory
Ethernet
MAC/PHY
Serial connectors
Expansion
prototype
connector
Expansion
prototype
connector
CompactFlash
connector
Mictor connector
JTAG connector
JTAG connector
Configuration
Four momentary contact switches for user input to the FPGA
Eight individual LEDs driven by the FPGA
Two seven-segment LEDs to display numeric output from the
FPGA
Two SRAM chips combined to form 1 Mbyte of fast, static
RAM
16 Mbytes of nonvolatile memory for use by both the FPGA
and the configuration controller
16 Mbytes of SDRAM
10/100 Ethernet MAC/PHY chip connected to an RJ-45
Ethernet connector
Two serial connectors with 5 V-tolerant buffers. Supports all
RS-232 signals.
Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.
Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.
CompactFlash connector for memory expansion
Mictor connector for debugging Nios II systems using a First
Silicon Solutions (FS2) debug probe.
Connects to the FPGA allowing hardware configuration from
Quartus II software and software debug from the Nios II IDE.
Connects to the configuration controller
Altera EPM7128AE device used to configure the FPGA from
2–6
controller
flash memory
Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition
July 2005
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